欢迎访问ic37.com |
会员登录 免费注册
发布采购

NZ48F4000L0ZBQ0 参数 Datasheet PDF下载

NZ48F4000L0ZBQ0图片预览
型号: NZ48F4000L0ZBQ0
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8 ?伏?英特尔? StrataFlash㈢ ?无线存储器?与? 3.0伏? I / O ? ( L30 ) [1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30)]
分类和应用: 存储无线
文件页数/大小: 100 页 / 1405 K
品牌: INTEL [ INTEL ]
 浏览型号NZ48F4000L0ZBQ0的Datasheet PDF文件第25页浏览型号NZ48F4000L0ZBQ0的Datasheet PDF文件第26页浏览型号NZ48F4000L0ZBQ0的Datasheet PDF文件第27页浏览型号NZ48F4000L0ZBQ0的Datasheet PDF文件第28页浏览型号NZ48F4000L0ZBQ0的Datasheet PDF文件第30页浏览型号NZ48F4000L0ZBQ0的Datasheet PDF文件第31页浏览型号NZ48F4000L0ZBQ0的Datasheet PDF文件第32页浏览型号NZ48F4000L0ZBQ0的Datasheet PDF文件第33页  
28F640L30, 28F128L30, 28F256L30  
boundary, the worst case output delay is one clock cycle less than the first access Latency Count.  
This delay can take place only once, and doesn’t occur if the burst sequence does not cross a  
device-row boundary. WAIT informs the system of this delay when it occurs.  
4.3.9  
Burst Length  
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the  
flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word.  
Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see  
Table 11, “Burst Sequence Word Ordering” on page 28). When a burst cycle begins, the device  
outputs synchronous burst data until it reaches the end of the “burstable” address space.  
Datasheet  
29