28F640L30, 28F128L30, 28F256L30
boundary, the worst case output delay is one clock cycle less than the first access Latency Count.
This delay can take place only once, and doesn’t occur if the burst sequence does not cross a
device-row boundary. WAIT informs the system of this delay when it occurs.
4.3.9
Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the
flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see
Table 11, “Burst Sequence Word Ordering” on page 28). When a burst cycle begins, the device
outputs synchronous burst data until it reaches the end of the “burstable” address space.
Datasheet
29
INTEL [ INTEL ]
