28F640L30, 28F128L30, 28F256L30
4.0
Read Operations
The device supports two read modes: asynchronous page mode and synchronous burst mode.
Asynchronous page mode is the default read mode after device power-up or a reset. The Read
Configuration Register must be configured to enable synchronous burst reads of the flash memory
array (see Section 4.3, “Read Configuration Register (RCR)” on page 23).
Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read
Status or Read Query. Upon power-up, or after a reset, all partitions of the device default to Read
Array. To change a partition’s read state, the appropriate read command must be written to the
device (see Section 3.2, “Device Commands” on page 18). See Section 9.0, “Special Read States”
on page 47 for details regarding Read Status, Read ID, and CFI Query modes.
The following sections describe read-mode operations in detail.
4.1
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read mode and all
partitions are set to Read Array. However, to perform array reads after any other device operation
(e.g. write operation), the Read Array command must be issued in order to read from the flash
memory array.
Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR[15] is set (see Section 4.3, “Read Configuration Register (RCR)” on page 23).
To perform an asynchronous page-mode read, an address is driven onto A[MAX:0], and CE# and
ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is de-asserted
during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held
low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored.
If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT
signal can be floated and ADV# must be tied to ground. Array data is driven onto D[15:0] after an
initial access time tAVQV delay. (see Section 12.0, “AC Characteristics” on page 55).
In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buffer. The buffer word corresponding to the initial address
on A[MAX:0] is driven onto D[15:0] after the initial access delay. Address bits A[MAX:2] select
the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the
data buffer at any given time.
4.2
Synchronous Burst-Mode Read
Read Configuration register bits CR[15:0] must be set before synchronous burst operation can be
performed. Synchronous burst mode can be performed for both array and non-array reads such as
Read ID, Read Status or Read Query. (See Section 4.3, “Read Configuration Register (RCR)” on
page 23 for details). Synchronous burst mode outputs 4-, 8-, 16-, or continuous-words. To perform
a synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and ADV# are
asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then
deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access,
in which case the address is latched on the next valid CLK edge while ADV# is asserted.
22
Datasheet
INTEL [ INTEL ]
