28F640L30, 28F128L30, 28F256L30
Table 10. WAIT Summary Table
CONDITION
WAIT
CE# = VIH
CE# = VIL
High-Z
Active
OE# = VIH
OE# = VIL
High-Z
Active
Synchronous Array Reads
Active
Active
Synchronous Non-Array Reads
All Asynchronous Reads and all Writes De-asserted
NOTE: Active: WAIT is asserted until data becomes valid, then de-asserts
4.3.4
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid
on D[15:0] for one or two clock cycles. This period of time is called the “data cycle”. When DH is
set, output data is held for two clocks (default). When DH is cleared, output data is held for one
clock (see Figure 6). The processor’s data setup time and the flash memory’s clock-to-data output
delay should be considered when determining whether to hold output data for one or two clocks.
A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition must be
satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
t
DATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4ns. Applying these values to the formula above:
20 ns + 4 ns ≤ 25 ns
The equation is satisfied and data will be available at every clock period with data hold setting at
one clock.
If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods must be
used.
Figure 6. Data Hold Timing
CLK [C]
D[15:0] [Q]
D[15:0] [Q]
1 CLK
Data Hold
Valid
Output
Valid
Output
Valid
Output
2 CLK
Data Hold
Valid
Output
Valid
Output
Datasheet
27
INTEL [ INTEL ]
