28F640L30, 28F128L30, 28F256L30
Table 6. Command Codes and Definitions (Sheet 2 of 2)
Mode
Code Device Mode
Description
First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. If the
next command is not Block Lock (0x01), Block Unlock (0xD0), or Block Lock-Down (0x2F), the
CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error.
Lock Block
0x60
Setup
Block
Locking/
Unlocking
0x01 Lock Block
If the previous command was Block Lock Setup (0x60), the addressed block is locked.
If the previous command was Block Lock Setup (0x60), the addressed block is unlocked. If the
addressed block is in a lock-down state, the operation has no effect.
0xD0 Unlock Block
Lock-Down
0x2F
If the previous command was Block Lock Setup (0x60), the addressed block is locked down.
Block
Program
Protection
Register
Setup
First cycle of a 2-cycle command; prepares the device for a Protection Register or Lock
Register program operation. The second cycle latches the register address and data, and starts
the programming algorithm
Protection 0xC0
Read
First cycle of a 2-cycle command; prepares the CUI for device read configuration. If the Set
Read Configuration Register command (0x03) is not the next command, the CUI sets Status
Register bits SR[4] and SR[5], indicating a command sequence error.
Configuration
Register
Setup
0x60
Configu-
ration
Read
If the previous command was Read Configuration Register Setup (0x60), the CUI latches the
0x03 Configuration address and writes A[15:0] to the Read Configuration Register. Following a Configure Read
Register Configuration Register command, subsequent read operations access array data.
Datasheet
21
INTEL [ INTEL ]
