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NZ48F4000L0ZBQ0 参数 Datasheet PDF下载

NZ48F4000L0ZBQ0图片预览
型号: NZ48F4000L0ZBQ0
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8 ?伏?英特尔? StrataFlash㈢ ?无线存储器?与? 3.0伏? I / O ? ( L30 ) [1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30)]
分类和应用: 存储无线
文件页数/大小: 100 页 / 1405 K
品牌: INTEL [ INTEL ]
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28F640L30, 28F128L30, 28F256L30  
Table 7. Read Configuration Register Description (Sheet 2 of 2)  
15  
Read Mode (RM)  
0 = Synchronous burst-mode read  
1 = Asynchronous page-mode read (default)  
14  
Reserved (R)  
Reserved bits should be cleared (0)  
13:11 Latency Count (LC[2:0])  
010 =Code 2  
011 =Code 3  
100 =Code 4  
101 =Code 5  
110 =Code 6  
111 =Code 7 (default)  
(Other bit settings are reserved)  
10  
9
Wait Polarity (WP)  
Data Hold (DH)  
0 =WAIT signal is active low  
1 =WAIT signal is active high (default)  
0 =Data held for a 1-clock data cycle  
1 =Data held for a 2-clock data cycle (default)  
8
Wait Delay (WD)  
Burst Sequence (BS)  
Clock Edge (CE)  
0 =WAIT de-asserted with valid data  
1 =WAIT de-asserted one data cycle before valid data (default)  
7
0 =Reserved  
1 =Linear (default)  
6
0 = Falling edge  
1 = Rising edge (default)  
5:4  
3
Reserved (R)  
Reserved bits should be cleared (0)  
Burst Wrap (BW)  
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]  
1 =No Wrap; Burst accesses do not wrap within burst length (default)  
2:0  
Burst Length (BL[2:0])  
001 =4-word burst  
010 =8-word burst  
011 =16-word burst  
111 =Continuous-word burst (default)  
(Other bit settings are reserved)  
NOTE: Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) Wait must be de-asserted with valid data (WD =  
0). Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) Wait de-asserted one data cycle before valid  
data (WD = 1) combination is not supported.  
4.3.1  
4.3.2  
Read Mode  
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation  
for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is  
cleared, synchronous burst mode is selected.  
Latency Count  
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the  
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data  
word is to be driven onto D[15:0]. The input clock frequency is used to determine this value.  
Figure 4 shows the data output latency for the different settings of LC[2:0].  
Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however,  
a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and  
Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word  
boundary is crossed. If CR.[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition  
will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT  
states.  
24  
Datasheet