28F640L30, 28F128L30, 28F256L30
Table 9. LC and Frequency Support for Bin 2 tAVQV/tCHQV (110ns / 20ns)
Latency Count Settings
Frequency Support (MHz)
2
≤ 22
≤ 33
≤40
3
4, 5, 6, or 7
See Figure 5, “Example Latency Count Setting using Code 3.
Figure 5. Example Latency Count Setting using Code 3
tData
0
1
2
3
4
CLK
CE#
ADV#
Address
A[MAX:0]
Code 3
High-Z
Data
D[15:0]
R103
4.3.3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is asserted-low.
WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted,
RST# deasserted).
4.3.3.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(CR[15]=0). The WAIT signal is only “de-asserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read status, read ID, or
read query. The WAIT signal is also “de-asserted” when data is valid on the bus.
When the device is operating in asynchronous page mode, asynchronous single word read mode,
and all write operations, WAIT is set to a de-asserted state as determined by CR[10]. See Figure 14,
“Asynchronous Single-Word Read (ADV# Latch)” on page 57, and Figure 15, “Asynchronous
Page-Mode Read Timing” on page 57.
26
Datasheet
INTEL [ INTEL ]
