28F640L30, 28F128L30, 28F256L30
3.3
Command Definitions
Valid device command codes and descriptions are shown in Table 6.
Table 6. Command Codes and Definitions (Sheet 1 of 2)
Mode
Code Device Mode
Description
Places the addressed partition in Read Array mode. Array data is output on D[15:0].
0xFF Read Array
Read Status Places the addressed partition in Read Status Register mode. The partition enters this mode
0x70
0x90
Register
after a program or erase command is issued. Status Register data is output on D[7:0].
Read Device
ID or
Configuration
Register
Places the addressed partition in Read Device Identifier mode. Subsequent reads from
addresses within the partition outputs manufacturer/device codes, Configuration Register data,
Block Lock status, or Protection Register data on D[15:0].
Read
Places the addressed partition in Read Query mode. Subsequent reads from the partition
addresses output Common Flash Interface information on D[7:0].
0x98 Read Query
Clear Status The WSM can only set Status Register error bits. The Clear Status Register command is used
0x50
Register
to clear the SR error bits.
First cycle of a 2-cycle programming command; prepares the CUI for a write operation. On the
next write cycle, the address and data are latched and the WSM executes the programming
algorithm at the addressed location. During program operations, the partition responds only to
Read Status Register and Program Suspend commands. CE# or OE# must be toggled to
update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the
Status Register Data for synchronous Non-array read. The Read Array command must be
issued to read array data after programming has finished.
Word Program
Setup
0x40
AlternateWord
0x10 Program
Setup
Equivalent to the Word Program Setup command, 0x40.
Buffered
0xE8
This command loads a variable number of bytes up to the buffer size of 32 words onto the
program buffer.
Write
Program
Buffered
0xD0 Program
Confirm
The confirm command is Issued after the data streaming for writing into the buffer is done. This
instructs the WSM to perform the Buffered Program algorithm, writing the data from the buffer
to the flash memory array.
Buffered
Enhanced
0x80 Factory
Programming
Setup
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode
(Buffered EFP). The CUI then waits for the Buffered EFP Confirm command, 0xD0, that
initiates the Buffered EFP algorithm. All other commands are ignored when Buffered EFP mode
begins.
Buffered EFP If the previous command was Buffered EFP Setup (0x80), the CUI latches the address and
0xD0
Confirm
data, and prepares the device for Buffered EFP mode.
First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The WSM
performs the erase algorithm on the block addressed by the Erase Confirm command. If the
next command is not the Erase Confirm (0xD0) command, the CUI sets Status Register bits
SR[4] and SR[5], and places the addressed partition in read status register mode.
Block Erase
Setup
0x20
Erase
If the first command was Block Erase Setup (0x20), the CUI latches the address and data, and
the WSM erases the addressed block. During block-erase operations, the partition responds
only to Read Status Register and Erase Suspend commands. CE# or OE# must be toggled to
update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the
Status Register Data for synchronous Non-array read.
Block Erase
Confirm
0xD0
This command issued to any device address initiates a suspend of the currently-executing
program or block erase operation. The Status Register indicates successful suspend operation
by setting either SR[2] (program suspended) or SR[6] (erase suspended), along with SR[7]
(ready). The Write State Machine remains in the suspend mode regardless of control signal
states (except for RST# asserted).
Program or
0xB0 Erase
Suspend
Suspend
Suspend
Resume
This command issued to any device address resumes the suspended program or block-erase
operation.
0xD0
20
Datasheet
INTEL [ INTEL ]
