1-Gbit P30 Family
Figure 21.
Synchronous Burst-Mode Four-Word Read Timing
R302
R301
R306
CLK [C]
Address [A]
ADV# [V]
R2
R101
A
R105
R102
R106
R303
R3
R8
R9
CE# [E]
OE# [G]
WAIT [T]
R15
R17
R307
R4
R304
R305
Q0
R7
R304
R10
Q3
Data [D/Q]
Q1
Q2
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0, Wait asserted low).
7.4
AC Write Specifications
Table 18.
AC Write Specifications (Sheet 1 of 2)
Num
Symbol
tPHWL
Parameter
Min
Max
Units
Notes
W1
W2
W3
W4
W5
W6
W7
W8
W9
RST# high recovery to WE# low
CE# setup to WE# low
150
0
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,3
1,2,4
tELWL
tWLWH
tDVWH
tAVWH
tWHEH
tWHDX
tWHAX
tWHWL
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
50
50
50
0
1,2
0
0
20
200
0
1,2,5
W10 tVPWH
W11 tQVVL
W12 tQVBL
W13 tBHWH
V
V
setup to WE# high
PP
PP
1,2,3,7
hold from Status read
WP# hold from Status read
WP# setup to WE# high
0
1,2,3,7
200
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
41
INTEL [ INTEL ]
