1-Gbit P30 Family
Figure 16.
Asynchronous Single-Word Read (ADV# Low)
R1
R2
R3
Address [A]
ADV#
R8
CE# [E}
OE# [G]
WAIT [T]
R4
R9
R15
R17
R7
R6
Data [D/Q]
RST# [P]
R5
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).
Figure 17.
Asynchronous Single-Word Read (ADV# Latch)
R1
R2
Address [A]
A[1:0][A]
R101
R105
R106
ADV#
CE# [E}
OE# [G]
WAIT [T]
R3
R8
R4
R9
R15
R17
R7
R6
R10
Data [D/Q]
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).
April 2005
38
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
INTEL [ INTEL ]
