1-Gbit P30 Family
Figure 18.
Asynchronous Page-Mode Read Timing
R1
R2
A[Max:2] [A]
A[1:0]
R101
R105
R106
ADV#
CE# [E]
R3
R8
R4
R10
OE# [G]
R15
R17
WAIT [T]
DATA [D/Q]
R7
R9
R108
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).
Figure 19.
Synchronous Single-Word Array or Non-array Read Timing
R301
R306
CLK [C]
R2
Address [A]
ADV# [V]
R101
R104
R106
R105
R303
R102
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R7
R9
R15
R307
R304
R17
R312
R4
R305
Data [D/Q]
1.
2.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to
assert either during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is
terminated by CE# deassertion after the first word in the burst.
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
39
INTEL [ INTEL ]
