1-Gbit P30 Family
Figure 23.
Asynchronous Read-to-Write Timing
R1
R2
W5
W8
Address [A]
CE# [E}
R3
R8
R9
R4
OE# [G]
WE# [W]
WAIT [T]
W2
W3
W6
R15
R17
R10
R7
R6
W7
W4
Data [D/Q]
RST# [P]
Q
D
R5
Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE#
deasserted.
Figure 24.
Write-to-Asynchronous Read Timing
W5
W8
R1
Address [A]
ADV# [V]
W2
W6
R10
CE# [E}
WE# [W]
OE# [G]
WAIT [T]
W3
W18
W14
R15
R17
R4
R2
R3
R8
W4
W7
R9
Data [D/Q]
RST# [P]
D
Q
W1
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
43