1-Gbit P30 Family
Figure 25.
Synchronous Read-to-Write Timing
Latency Count
R301
R302
R306
CLK [C]
Address [A]
ADV# [V]
R2
W5
R101
W18
R105
R102
R106
R104
R303
R11
R13
R3
W6
CE# [E]
OE# [G]
R4
R8
W21
W22
W21
W22
W2
W8
W15
W3
W9
WE#
R16
R307
R304
R312
WAIT [T]
R7
R305
W7
Q
D
D
Data [D/Q]
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). Clock is
ignored during write operation.
Figure 26.
Write-to-Synchronous Read Timing
R302
R301
R2
CLK
W5
W8
R306
R106
Address [A]
R104
R303
ADV#
W6
W2
R11
CE# [E}
W18
W19
W20
W3
WE# [W]
OE# [G]
WAIT [T]
R4
R15
R3
R307
W7
R304
R305
R304
W4
D
Q
Q
Data [D/Q]
RST# [P]
W1
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low).
April 2005
44
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
INTEL [ INTEL ]
