1-Gbit P30 Family
Table 16.
AC Read Specifications for 64/128-Mbit Densities (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
R305
R306
tCHQX
tCHAX
tCHTV
tCHVL
tCHTX
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
3
10
-
-
-
ns
ns
ns
ns
ns
1,5
1,4,5
1,5
1
R307
20
-
R311
CLK Valid to ADV# Setup
WAIT Hold from CLK
3
R312
3
-
1,5
NOTES:
1.
See Figure 13, “AC Input/Output Reference Waveform” on page 33 for timing measurements and max allowable input
slew rate.
2.
3.
4.
5.
6.
OE# may be delayed by up to t
Sampled, not 100% tested.
Address hold in synchronous burst mode is t
Applies only to subsequent synchronous reads.
See your local Intel representative for designs requiring higher than 40 MHz synchronous operation.
– t
after CE#’s falling edge without impact to t
.
ELQV
GLQV
ELQV
or t
, whichever timing specification is satisfied first.
CHAX
VHAX
Table 17.
AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 1 of 2)
Num
Symbol
Parameter
Speed
Min
Max
Unit
Notes
Asynchronous Specifications
Vcc = 1.8 V – 2.0 V
Vcc = 1.7 V – 2.0 V
Vcc = 1.8 V – 2.0 V
Vcc = 1.7 V – 2.0 V
Vcc = 1.8 V – 2.0 V
Vcc = 1.7 V – 2.0 V
85
88
-
-
-
R1
R2
R3
tAVAV
tAVQV
tELQV
Read cycle time
ns
ns
ns
85
88
85
88
25
150
-
Address to output valid
CE# low to output valid
-
-
-
R4
R5
OE# low to output valid
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
-
R6
0
0
-
1,3
1,2,3
R7
-
R8
24
24
-
R9
-
1,3
R10
R11
R12
R13
R15
R16
R17
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
0
20
-
tEHEL
tELTV
tEHTZ
tGLTV
tGLTX
tGHTZ
-
1
CE# low to WAIT valid
17
20
17
-
CE# high to WAIT high-Z
-
1,3
1
OE# low to WAIT valid
-
OE# low to WAIT in low-Z
0
-
1,3
OE# high to WAIT in high-Z
20
Latching Specifications
April 2005
36
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
INTEL [ INTEL ]
