Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 7.
PCI Controller (Sheet 2 of 2)
Power
Name
on
Reset2 Type†
Description
Reset1
PCI Device Select:
•
When used as an output, PCI_DEVSEL_N indicates that
device has decoded that address as the target of the
requested transaction.
PCI_DEVSEL_N
Z
Z
I/O
•
When used as an input, PCI_DEVSEL_N indicates if any
device on the PCI bus exists with the given address.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Initialization Device Select is a chip select during
configuration reads and writes.
PCI_IDSEL
Z
Z
Z
Z
I
I
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI arbitration request: Used by the internal PCI arbiter to allow
an agent to request the PCI bus.
PCI_REQ_N[3:1]
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI arbitration request:
•
When configured as an input (PCI arbiter enabled), the
internal PCI arbiter will allow an agent to request the PCI
bus.
PCI_REQ_N[0]
PCI_GNT_N[3:1]
PCI_GNT_N[0]
Z
Z
Z
Z
Z
Z
I/O
O
•
When configured as an output (PCI arbiter disabled), the pin
will be used to request access to the PCI bus from an
external arbiter.
Should be pulled high with a 10-KΩ resistor, when the PCI bus is
not being utilized in the system.
PCI arbitration grant: Generated by the internal PCI arbiter to
allow an agent to claim control of the PCI bus.
PCI arbitration grant:
•
When configured as an output (PCI arbiter enabled), the
internal PCI arbiter to allow an agent to claim control of the
PCI bus.
I/O
•
When configured as an input (PCI arbiter disabled), the pin
will be used to claim access of the PCI bus from an external
arbiter.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI interrupt: Used to request an interrupt.
PCI_INTA_N
PCI_CLKIN
Z
Z
Z
O/D
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Clock: provides timing for all transactions on PCI. All PCI
signals — except INTA#, INTB#, INTC#, and INTD# — are
sampled on the rising edge of CLK and timing parameters are
defined with respect to this edge. The PCI clock rate can operate
at up to 66 MHz.
VI
I
Should be pulled low with a 10-KΩ resistor when not being
utilized in the system.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
Datasheet
March 2005
37
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
