Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 6.
SDRAM Interface (Sheet 2 of 2)
Power
Name
on
Reset2 Type†
Description
Reset1
SDRAM Clock Enable: CKE is driving high to activate the
clock to an external SDRAM and driven low to de-activate the
CLK to an external SDRAM.
SDM_CKE
Z
Z
1
0
O
O
SDRAM Data bus mask: DQM is used to byte select data
during read/write access to an external SDRAM.
SDM_DQM[3:0]
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
Datasheet
March 2005
35
Document Number: 252479, Revision: 005
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