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GWIXP425BDT 参数 Datasheet PDF下载

GWIXP425BDT图片预览
型号: GWIXP425BDT
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内容描述: 网络处理器Intel㈢ IXP42X产品线和IXC1100控制平面处理器 [Intel㈢ IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor]
分类和应用:
文件页数/大小: 134 页 / 1072 K
品牌: INTEL [ INTEL ]
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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor  
Table 8.  
High-Speed, Serial Interface 0  
Power  
Name  
On  
Reset2 Type†  
Description  
Reset1  
The High-Speed Serial (HSS) transmit frame signal can be  
configured as an input or an output to allow an external  
source become synchronized with the transmitted data. Often  
known as a Frame Sync signal. Configured as an input upon  
reset.  
HSS_TXFRAME0  
HSS_TXDATA0  
Z
Z
Z
Z
I/O  
Should be pulled low with a 10-Kresistor when not being  
utilized in the system.  
Transmit data out. Open Drain output.  
O/D  
Must be pulled high with a 10-Kresistor to VCCP  
.
The High-Speed Serial (HSS) transmit clock signal can be  
configured as an input or an output. The clock can be a  
frequency ranging from 512 KHz to 8.192 MHz. Used to clock  
out the transmitted data. Configured as an input upon reset.  
Frame sync and data can be selected to be generated on the  
rising or falling edge of the transmit clock.  
HSS_TXCLK0  
Z
Z
Z
Z
I/O  
I/O  
Should be pulled low with a 10-Kresistor when not being  
utilized in the system.  
The High-Speed Serial (HSS) receive frame signal can be  
configured as an input or an output to allow an external  
source to become synchronized with the received data. Often  
known as a Frame Sync signal. Configured as an input upon  
reset.  
HSS_RXFRAME0  
Should be pulled low with a 10-Kresistor when not being  
utilized in the system.  
Receive data input. Can be sampled on the rising or falling  
edge of the receive clock.  
HSS_RXDATA0  
HSS_RXCLK0  
Z
Z
VI  
Z
I
Should be pulled low through a 10-Kresistor when not  
being utilized in the system.  
The High-Speed Serial (HSS) receive clock signal can be  
configured as an input or an output. The clock can be from  
512 KHz to 8.192 MHz. Used to sample the received data.  
Configured as an input upon reset.  
I/O  
Should be pulled low with a 10-Kresistor when not being  
utilized in the system.  
1.  
2.  
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.  
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of  
PLL_LOCK, all signals reflect the value shown in the RESET column.  
For a legend of the Type codes, see Table 5 on page 33.  
March 2005  
38  
Datasheet  
Document Number: 252479, Revision: 005