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GWIXP425BDT 参数 Datasheet PDF下载

GWIXP425BDT图片预览
型号: GWIXP425BDT
PDF下载: 下载PDF文件 查看货源
内容描述: 网络处理器Intel㈢ IXP42X产品线和IXC1100控制平面处理器 [Intel㈢ IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor]
分类和应用:
文件页数/大小: 134 页 / 1072 K
品牌: INTEL [ INTEL ]
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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor  
3.0  
Functional Signal Descriptions  
Listed in the signal definition tables — starting at Table 6 “SDRAM Interface” on page 34 — are  
pull-up an pull-down resistor recommendations that are required when the particular enabled  
interface is not being used in the application. These external resistor requirements are only needed  
if the particular model of Intel® IXP42X product line and IXC1100 control plane processors has  
the particular interface enabled and the interface is not required in the application.  
Warning:  
All IXP42X product line and IXC1100 control plane processors I/O pins are not 5-V tolerant.  
Disabled features, within the IXP42X product line and IXC1100 control plane processors, do not  
require external resistors as the processor will have internal pull-up or pull-down resistors enabled  
as part of the disabled interface.  
Table 5 presents the legend for interpreting the Type field in the other tables in this section of the  
document.  
To determine which interfaces are not enabled within the IXP42X product line and IXC1100  
control plane processors, see Table 3 on page 14.  
Table 5.  
Signal Type Definitions  
Symbol  
Description  
I
O
Input pin only  
Output pin only  
I/O  
OD  
PWR  
GND  
1
Pin can be either an input or output  
Open Drain pin  
Power pin  
Ground pin  
Driven to Vcc  
0
Driven to Vss  
X
Driven to unknown state  
Input is disabled  
ID  
H
Pulled up to Vcc  
L
Pulled to Vss  
PD  
Z
Pull-up Disabled  
Output Disabled  
VO  
VI  
A valid output level is driven, allowed states -- 1, 0, H, Z  
Need to drive a valid input level, allowed states - 1, 0, H, Z  
Pull-up Enabled, equivalent to H  
Output Only/Tristatable  
No Connect  
PE  
Tri  
N/C  
-
Pin must be connected as described  
Other tables in this section include:  
Table 6 SDRAM Interface signals  
Table 7 PCI Controller signals  
Datasheet  
March 2005  
33  
Document Number: 252479, Revision: 005