Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 7.
PCI Controller (Sheet 1 of 2)
Power
Name
on
Reset2 Type†
Description
Reset1
PCI Address/Data bus used to transfer address and bidirectional
data to and from multiple PCI devices.
PCI_AD[31:0]
Z
Z
Z
Z
Z
Z
I/O
I/O
I/O
Should be pulled low with a 10-KΩ resistor when not being
utilized in the system.
PCI Command/Byte Enables is used as a command word during
PCI address cycles and as byte enables for data cycles.
PCI_CBE_N[3:0]
PCI_PAR
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Parity used to check parity across the 32 bits of PCI_AD and
the four bits of PCI_CBE_N.
Should be pulled low with a 10-KΩ resistor when not being
utilized in the system.
PCI Cycle Frame used to signify the beginning and duration of a
transaction. The signal will be inactive prior to or during the final
data phase of a given transaction.
PCI_FRAME_N
Z
Z
I/O
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Target Ready informs that the target of the PCI bus is ready
to complete the current data phase of a given transaction.
PCI_TRDY_N
PCI_IRDY_N
PCI_STOP_N
Z
Z
Z
Z
Z
Z
I/O
I/O
I/O
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Initiator Ready informs the PCI bus that the initiator is ready
to complete the transaction.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Stop indicates that the current target is requesting the
current initiator to stop the current transaction.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Parity Error asserted when a PCI parity error is detected —
between the PCI_PAR and associated information on the
PCI_AD bus and PCI_CBE_N — during all PCI transactions,
except for Special Cycles. The agent receiving data will drive this
signal.
PCI_PERR_N
PCI_SERR_N
Z
Z
Z
Z
I/O
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI System Error asserted when a parity error occurs on special
cycles or any other error that will cause the PCI bus not to
function properly. This signal can function as an input or an open
drain output.
I/OD
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
March 2005
36
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
