Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 9.
High-Speed, Serial Interface 1
Power
Name
On
Reset2 Type†
Description
Reset1
The High-Speed Serial (HSS) transmit frame signal can be
configured as an input or an output to allow an external
source to be synchronized with the transmitted data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
HSS_TXFRAME1
HSS_TXDATA1
Z
Z
Z
Z
I/O
Should be pulled low with a 10-KΩ resistor when not being
utilized in the system.
Transmit data out. Open Drain output.
O/D
Must be pulled high with a 10-KΩ resistor to VCCP
.
The High-Speed Serial (HSS) transmit clock signal can be
configured as an input or an output. The clock can be a
frequency ranging from 512 KHz to 8.192 MHz. Used to
clock out the transmitted data. Configured as an input upon
reset. Frame sync and Data can be selected to be generated
on the rising or falling edge of the transmit clock.
HSS_TXCLK1
Z
Z
Z
Z
I/O
I/O
Should be pulled low with a 10-KΩ resistor when not being
utilized in the system.
The High-Speed Serial (HSS) receive frame signal can be
configured as an input or an output to allow an external
source to be synchronized with the received data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
HSS_RXFRAME1
Should be pulled low with a 10-KΩ resistor when not being
utilized in the system.
Receive data input. Can be sampled on the rising or falling
edge of the receive clock.
HSS_RXDATA1
HSS_RXCLK1
Z
Z
VI
Z
I
Should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
The High-Speed Serial (HSS) receive clock signal can be
configured as an input or an output. The clock can be from
512 KHz to 8.192 MHz. Used to sample the received data.
Configured as an input upon reset.
I/O
Should be pulled low with a 10-KΩ resistor when not being
utilized in the system.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
Datasheet
March 2005
39
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
