Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 10.
MII Interfaces (Sheet 2 of 2)
Power
Name
On
Reset2 Type†
Description
Reset1
Management data clock. Management data interface clock
is used to clock the MDIO signal as an output and sample
the MDIO as an input. The ETH_MDC is an input on power
up and can be configured to be an output through an Intel
API as documented in the Intel® IXP400 Software
Programmer’s Guide.
ETH_MDC
Z
Z
Z
O
Externally supplied transmit clock.
•
•
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
ETH_TXCLK1
VI
I
Should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
Transmit data bus to PHY, asserted synchronously with
respect to ETH_TXCLK1.
ETH_TXDATA1[3:0]
ETH_TXEN1
Z
Z
0
0
O
O
Indicates that the PHY is being presented with nibbles on
the MII interface. Asserted synchronously, with respect to
ETH_TXCLK1, at the first nibble of the preamble, and
remains asserted until all the nibbles of a frame are
presented.
Externally supplied receive clock.
•
•
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
ETH_RXCLK1
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
Receive data bus from PHY, data sampled synchronously,
with respect to ETH_RXCLK1.
ETH_RXDATA1[3:0]
ETH_RXDV1
Z
Z
Z
VI
VI
VI
I
I
I
•
Should be pulled low through a 10-KΩ resistor when
not being utilized in the system.
Receive data valid, used to inform the MII interface that the
Ethernet PHY is sending data.
Should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
Asserted by the PHY when a collision is detected by the
PHY.
ETH_COL1
•
Should be pulled low through a 10-KΩ resistor when
not being utilized in the system.
Asserted by the PHY when the transmit medium or receive
medium are active. De-asserted when both the transmit
and receive medium are idle. Remains asserted throughout
the duration of collision condition. PHY asserts CRS
asynchronously and de-asserts synchronously with respect
to ETH_RXCLK1.
ETH_CRS1
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
Datasheet
March 2005
41
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
