Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 10.
MII Interfaces (Sheet 1 of 2)
Power
Name
On
Reset2 Type†
Description
Reset1
Externally supplied transmit clock.
•
•
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
ETH_TXCLK0
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
Transmit data bus to PHY, asserted synchronously with
respect to ETH_TXCLK0.
ETH_TXDATA0[3:0]
ETH_TXEN0
Z
Z
0
0
O
O
Indicates that the PHY is being presented with nibbles on
the MII interface. Asserted synchronously, with respect to
ETH_TXCLK0, at the first nibble of the preamble and
remains asserted until all the nibbles of a frame are
presented.
Externally supplied receive clock.
•
•
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
ETH_RXCLK0
Z
Z
VI
VI
I
I
Should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
Receive data bus from PHY, data sampled synchronously
with respect to ETH_RXCLK0
ETH_RXDATA0[3:0]
•
Should be pulled low through a 10-KΩ resistor when
not being utilized in the system.
Receive data valid, used to inform the MII interface that the
Ethernet PHY is sending data. Should be pulled low
through a 10-KΩ resistor when not being utilized in the
system.
ETH_RXDV0
ETH_COL0
Z
Z
VI
VI
I
I
Asserted by the PHY when a collision is detected by the
PHY. Should be pulled low through a 10-KΩ resistor when
not being utilized in the system.
Asserted by the PHY when the transmit medium or receive
medium is active. De-asserted when both the transmit and
receive medium are idle. Remains asserted throughout the
duration of a collision condition. PHY asserts CRS
asynchronously and de-asserts synchronously, with
respect to ETH_RXCLK0. Should be pulled low through a
10-KΩ resistor when not being utilized in the system.
ETH_CRS0
ETH_MDIO
Z
Z
VI
I
Management data output. Provides the write data to both
PHY devices connected to each MII interface.
An external 1.5-KΩ pull-up resistor is required.
Note:
If interfacing with a single Intel® LXT972 Fast Ethernet
Transceiver, and a 1.5K pull-up resistor is not used, the
NPE will ‘see’ 32 PHYs on the MII interface.
Z
I/O
Should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
March 2005
40
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
