Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
2.2.11
2.2.12
Performance Monitoring Unit (PMU)
The performance monitoring unit contains two 32-bit, event counters and one 32-bit, clock counter.
The event counters can be programmed to monitor I-cache hit rate, data caches hit rate, ITLB hit
rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count.
Debug Unit
The debug unit is accessed through the JTAG port. The industry-standard, IEEE 1149.1 JTAG port
consists of a test access port (TAP) controller, boundary-scan register, instruction and data
registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#.
The debug unit — when used with debugger application code running on a host system outside of
the Intel XScale core — allows a program, running on the Intel XScale core, to be debugged. It
allows the debugger application code or a debug exception to stop program execution and redirect
execution to a debug-handling routine.
Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug
breakpoint, exception vector trap, and trace buffer full breakpoint. Once execution has stopped, the
debugger application code can examine or modify the core’s state, coprocessor state, or memory.
The debugger application code can then restart program execution.
The debug unit has two hardware-instruction, break point registers; two hardware, data-breakpoint
registers; and a hardware, data-breakpoint control register. The second data-breakpoint register can
be alternatively used as a mask register for the first data-breakpoint register.
A 256-entry trace buffer provides the ability to capture control flow messages or addresses. A
JTAG instruction (LDIC) can be used to download a debug handler via the JTAG port to the mini-
instruction cache (the I-cache has a 2-Kbyte, mini-instruction cache to hold a debug handler).
March 2005
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Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
