DC & Switching Characteristics
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 5–15 through 5–22 describe the
MAX II device internal timing microparameters for logic elements (LEs),
TM
input/output elements (IOEs), UFM structures, and MultiTrack
interconnects.
f
For more explanations and descriptions on each internal timing
microparameters symbol, refer to the chapter on Understanding Timing in
MAX II Devices.
Table 5–15. LE Internal Timing Microparameters
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Symbol
Parameter
Unit
ps
ps
ps
ps
ps
ps
ps
ps
Min
Max
Min
Max
Min
Max
tLUT
LE combinational
LUT delay
571
742
914
tCLR
tPRE
tSU
LE register clear
delay
238
238
208
0
309
309
271
0
381
381
333
0
LE register preset
delay
LE register setup
time before clock
tH
LE register hold time
after clock
tCO
tCLKHL
tC
LE register clock-to-
output delay
235
857
305
376
Minimum clock high
or low time
166
216
266
Register control
delay
1,114
1,372
Table 5–16. IOE Internal Timing Microparameters (Part 1 of 2)
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
tFASTIO
Data output delay
from adjacent LE to
I/O block
159
207
254
ps
tIN
I/O input pad and
buffer delay
708
920
1,132
ps
Altera Corporation
July 2006
Core Version a.b.c variable
5–13
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
