DC & Switching Characteristics
Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 3)
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
Symbol
Parameter
Min
Max
Min
Max
Min
Max
tADH
Address register
data in hold from
address register
clock
20
20
20
ns
tDCLK
tDSS
Data register clock
period
100
60
100
60
100
60
ns
ns
Data register shift
signal setup to data
register clock
tDSH
tDDS
tDDH
Data register shift
signal hold from data
register clock
20
20
20
0
20
20
20
0
20
20
20
0
ns
ns
ns
Data register data in
setup to data register
clock
Data register data in
hold from data
register clock
tDP
tPB
Program signal to
data clock hold time
ns
ns
Maximum delay
between program
rising edge to UFM
busy signal rising
edge
960
960
960
tBP
Minimum delay
allowed from UFM
busy signal going
low to program
signal going low
20
20
20
ns
tPPMX
Maximum length of
busy pulse during a
program
100
960
100
960
100
960
μs
ns
ns
tAE
Minimum erase
signal to address
clock hold time
0
0
0
tEB
Maximum delay
between the erase
rising edge to the
UFM busy signal
rising edge
Altera Corporation
July 2006
Core Version a.b.c variable
5–17
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
