Timing Model & Specifications
MAX II devices timing can be analyzed with the Altera Quartus II
software, a variety of popular industry-standard EDA simulators and
timing analyzers, or with the timing model shown in Figure 5–2.
Timing Model &
Specifications
MAX II devices have predictable internal delays that enable the designer
to determine the worst-case timing of any design. The software provides
timing simulation, point-to-point delay prediction, and detailed timing
analysis for device-wide performance evaluation.
Figure 5–2. MAX II Device Timing Model
Output & Output Enable
Data Delay
tR4
tIODR
tIOE
Data-In/LUT Chain
Output Routing
Delay
User
Flash
Memory
Logic Element
LUT Delay
tLUT
Output
Delay
tOD
tXZ
tZX
tC4
tFASTIO
tCO
tSU
Input Routing
Delay
tH
I/O Input Delay
Register Control
Delay
I/O Pin
tPRE
tCLR
tIN
tDL
tC
From Adjacent LE
tGLOB
INPUT
I/O Pin
Global Input Delay
To Adjacent LE
Register Delays
Data-Out
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Refer to the chapter on Understanding
Timing in MAX II Devices for more information.
This section describes and specifies the performance, internal, external,
and UFM timing specifications. All specifications are representative of
worst-case supply voltage and junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The
Quartus® II software issues an informational message during the design
compilation if the timing models are preliminary. Table 5–13 shows the
status of the MAX II device timing models.
5–10
Core Version a.b.c variable
Altera Corporation
July 2006
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
