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EPM1270GF100I4N 参数 Datasheet PDF下载

EPM1270GF100I4N图片预览
型号: EPM1270GF100I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 98 页 / 1060 K
品牌: INTEL [ INTEL ]
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Timing Model & Specifications  
Table 5–19. tXZ IOE Microparameter Adders for Fast Slew Rate (Part 2 of 2)  
-3 Speed Grade  
-4 Speed Grade  
-5 Speed Grade  
Standard  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
1.5-V LVTTL  
4 mA  
2 mA  
606  
673  
71  
788  
875  
93  
970  
1,077  
114  
ps  
ps  
ps  
3.3-V PCI  
20 mA  
Table 5–20. tXZ IOE MIcroparameter Adders for Slow Slew Rate  
-3 Speed Grade -4 Speed Grade  
-5 Speed Grade  
Standard  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
3.3-V LVCMOS  
8 mA  
4 mA  
206  
891  
206  
891  
222  
943  
161  
–20  
665  
–20  
665  
–4  
–247  
438  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
3.3-V LVTTL  
2.5-V LVTTL  
3.3-V PCI  
16 mA  
8 mA  
–247  
438  
14 mA  
7 mA  
–231  
490  
717  
210  
20 mA  
258  
Table 5–21. UFM Block Internal Timing Microparameters (Part 1 of 3)  
-3 Speed Grade  
-4 Speed Grade  
-5 Speed Grade  
Symbol  
Parameter  
Unit  
ns  
Min  
Max  
Min  
Max  
Min  
Max  
tACLK  
tASU  
Address register  
clock period  
100  
100  
100  
Address register  
shift signal setup to  
address register  
clock  
20  
20  
20  
20  
20  
20  
20  
20  
20  
ns  
tAH  
Address register  
shift signal hold to  
address register  
clock  
ns  
ns  
tADS  
Address register  
data in setup to  
address register  
clock  
5–16  
Core Version a.b.c variable  
Altera Corporation  
July 2006  
MAX II Device Handbook, Volume 1  
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