EPCS Device Memory Access
Page 21
The first byte address can be at any location. The device automatically increases the
address to the next higher address after shifting out each byte of data. Therefore, the
device can read the whole memory with a single read bytes operation. When the
device reaches the highest address, the address counter restarts at 0x000000, allowing
the memory contents to be read out indefinitely until the read bytes operation is
terminated by driving the nCSsignal high. The device can drive the nCSsignal high at
any time after data is shifted out. If the read bytes operation is shifted in while a write
or erase cycle is in progress, the operation is not executed and does not affect the write
or erase cycle in progress.
April 2014 Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
INTEL [ INTEL ]
