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EPCS1SI8 参数 Datasheet PDF下载

EPCS1SI8图片预览
型号: EPCS1SI8
PDF下载: 下载PDF文件 查看货源
内容描述: [Configuration Memory, 1MX1, Serial, CMOS, PDSO8, PLASTIC, SOIC-8]
分类和应用: 时钟光电二极管内存集成电路
文件页数/大小: 40 页 / 1107 K
品牌: INTEL [ INTEL ]
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EPCS Device Memory Access  
Page 19  
Table 12. Block Protection Bits in the EPCS64 Devices  
Status Register  
Content  
Memory Content  
BP2 BP1 BP0  
Protected Area  
Unprotected Area  
Bit  
0
Bit  
0
Bit  
0
None  
All sectors (128 sectors: 0 to 127)  
Lower 63/64ths (126 sectors: 0 to 125)  
Lower 31/32nds (124 sectors: 0 to 123)  
Lower 15/16ths (120 sectors: 0 to 119)  
Lower seven-eights (112 sectors: 0 to 111)  
Lower three-quarters (96 sectors: 0 to 95)  
Lower half (64 sectors: 0 to 63)  
None  
0
0
1
Upper 64th (2 sectors: 126 and 127)  
Upper 32nd (4 sectors: 124 to 127)  
Upper sixteenth (8 sectors: 120 to 127)  
Upper eighth (16 sectors: 112 to 127)  
Upper quarter (32 sectors: 96 to 127)  
Upper half (64 sectors: 64 to 127)  
All sectors (128 sectors: 0 to 127)  
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Table 13. Block Protection Bits in the EPCS128 Device  
Status Register  
Content  
Memory Content  
BP2 BP1 BP0  
Protected Area  
Unprotected Area  
Bit  
Bit  
Bit  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None  
All sectors (64 sectors—0 to 63)  
Lower 63/64ths (63 sectors—0 to 62)  
Lower 31/32nds (62 sectors—0 to 61)  
Lower 15/16ths (60 sectors—0 to 59)  
Lower seven-eighths (56 sectors—0 to 55)  
Lower three-quarters (48 sectors—0 to 47)  
Lower half (32 sectors—0 to 31)  
None  
Upper 64th (1 sector—63)  
Upper 32nd (2 sectors—62 to 63)  
Upper 16th (4 sectors—60 to 63)  
Upper 8th (8 sectors—56 to 63)  
Upper quarter (16 sectors—48 to 63)  
Upper half (32 sectors—32 to 63)  
All sectors (64 sectors—0 to 63)  
You can read the status register at any time, even during a write or erase cycle is in  
progress. When one of these cycles is in progress, you can check the write in progress  
bit (bit  
0of the status register) before sending a new operation to the device. The  
device can also read the status register continuously, as shown in Figure 9.  
Figure 9. Read Status Operation Timing Diagram  
nCS  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
DCLK  
ASDI  
DATA  
Operation Code  
Status Register Out  
Status Register Out  
High Impedance  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB  
MSB  
April 2014 Altera Corporation  
Serial Configuration (EPCS) Devices Datasheet  
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