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EPCS Device Memory Access
Table 9. Block Protection Bits in the EPCS1 Device
Status Register Content
Memory Content
BP1 Bit
BP0 Bit
Protected Area
Unprotected Area
All four sectors—0 to 3
Three sectors—0 to 2
Two sectors—0 and 1
None
0
0
1
1
0
1
0
1
None
Sector 3
Two sectors—2 and 3
All sectors
Table 10. Block Protection Bits in the EPCS4 Device
Status Register Content
Memory Content
Protected Area
BP2 Bit
BP1 Bit
BP0 Bit
Unprotected Area
All eight sectors—0 to 7
Seven sectors—0 to 6
Six sectors—0 to 5
Four sectors—0 to 3
None
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
Sector 7
Sectors 6 and 7
Four sectors—4 to 7
All sectors
All sectors
None
All sectors
None
All sectors
None
Table 11. Block Protection Bits in the EPCS16 Device
Status Register
Content
Memory Content
BP2
Bit
BP1
Bit
BP0
Bit
Protected Area
Unprotected Area
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
All sectors (32 sectors 0 to 31)
Lower 31/32nds (31 sectors—0 to 30)
Lower 15/16ths (30 sectors—0 to 29)
Lower seven-eighths (28 sectors—0 to 27)
Lower three-quarters (24 sectors—0 to 23)
Lower half (16 sectors—0 to 15)
None
Upper 32nd (Sector 31)
Upper sixteenth (two sectors—30 and 31)
Upper eighth (four sectors—28 to 31)
Upper quarter (eight sectors—24 to 31)
Upper half (sixteen sectors—16 to 31)
All sectors (32 sectors—0 to 31)
All sectors (32 sectors—0 to 31)
None
Serial Configuration (EPCS) Devices Datasheet
April 2014 Altera Corporation
INTEL [ INTEL ]
