EPCS Device Memory Access
Page 15
Table 8. EPCS Devices Operation Codes
DCLK fMAX
(1)
Operation
Erase sector
Operation Code
1101 1000
Address Bytes
Dummy Bytes
Data Bytes
(MHz)
3
0
0
2
0
25
Read device
identification
(2)
1001 1111
1 to infinite
25
(5)
Notes to Table 8:
(1) List MSB first and LSB last.
(2) The status register, data, or silicon ID is read out at least once on the DATApin and is continuously read out until the nCSpin is driven high.
(3) A write bytes operation requires at least one data byte on the DATApin. If more than 256 bytes are sent to the device, only the last 256 bytes
are written to the memory.
(4) The read silicon ID operation is available only for EPCS1, EPCS4, EPCS16, and EPCS64 devices.
(5) The read device identification operation is available only for EPCS128 devices.
Write Enable Operation
The write enable operation code is b'0000 0110, and it lists the MSB first. The write
enable operation sets the write enable latch bit, which is bit
1in the status register.
Always set the write enable latch bit before write bytes, write status, erase bulk, and
erase sector operations. Figure 5 shows the instruction sequence of the write enable
operation.
Figure 5. Write Enable Operation Timing Diagram
nCS
0
1
2
3
4
5
6
7
DCLK
ASDI
Operation Code
High Impedance
DATA
Write Disable Operation
The write disable operation code is b'0000 0100and it lists the MSB first. The write
disable operation resets the write enable latch bit, which is bit in the status register.
1
To prevent the memory from being written unintentionally, the write enable latch bit
is automatically reset when implementing the write disable operation, and under the
following conditions:
■
■
■
■
■
Power up
Write bytes operation completion
Write status operation completion
Erase bulk operation completion
Erase sector operation completion
April 2014 Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
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