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EPCS Device Memory Access
Figure 6 shows the instruction sequence of the write disable operation.
Figure 6. Write Disable Operation Timing Diagram
nCS
0
1
2
3
4
5
6
7
DCLK
ASDI
Operation Code
High Impedance
DATA
Read Status Operation
The read status operation code is b'0000 0101and it lists the MSB first. You can use
the read status operation to read the status register. Figure 7 and Figure 8 show the
status bits in the status register of the EPCS devices.
Figure 7. EPCS128, EPCS64, EPCS16, and EPCS4 Status Register Status Bits
Bit 7
Bit 0
BP2
BP1
BP0
WEL
WIP
Block Protect Bits [2..0]
Write In
Progress Bit
Write Enable
Latch Bit
Figure 8. EPCS1 Status Register Status Bits
Bit 7
Bit 0
WIP
BP1
BP0
WEL
Block Protect
Bits [1..0]
Write In
Progress Bit
Write Enable
Latch Bit
Setting the write in progress bit to
1indicates that the EPCS device is busy with a
write or erase cycle. Resetting the write in progress bit to
cycle is in progress.
0
indicates no write or erase
Serial Configuration (EPCS) Devices Datasheet
April 2014 Altera Corporation
INTEL [ INTEL ]
