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EPCS Device Memory Access
Table 7. Address Range for Sectors in EPCS128 Devices (Part 3 of 3)
Address Range (Byte Addresses in HEX)
Sector
Start
End
5
4
3
2
1
0
H'140000
H'100000
H'0C0000
H'080000
H'040000
H'000000
H'17FFFF
H'13FFFF
H'0FFFFF
H'0BFFFF
H'07FFFF
H'03FFFF
Operation Codes
This section describes the operations that you can use to access the memory in EPCS
devices. Use the DATA ASDI, and nCSsignals to access the memory in EPCS
,
DCLK,
devices. When performing the operation, addresses and data are shifted in and out of
the device serially, with MSB first.
The device samples the AS data input on the first rising edge of the DCLKafter the
active low chip select (nCS) input signal is driven low. Shift the operation code, with
MSB first, into the EPCS device serially through the AS data input (ASDI) pin. Each
operation code bit is latched into the EPCS device on the rising edge of the DCLK
.
Different operations require a different sequence of inputs. While executing an
operation, you must shift in the desired operation code, followed by the address bytes
or data bytes, both address and data bytes, or none of them. The device must drive
nCSpin high after the last bit of the operation sequence is shifted in. Table 8 lists the
operation sequence for every operation supported by the EPCS devices.
For read operations, the data read is shifted out on the DATApin. You can drive the nCS
pin high after any bit of the data-out sequence is shifted out.
For write and erase operations, drive the nCSpin high at a byte boundary that is in a
multiple of eight clock pulses. Otherwise, the operation is rejected and not executed.
All attempts to access the memory contents while a write or erase cycle is in progress
are rejected, and the write or erase cycle will continue unaffected.
Table 8. EPCS Devices Operation Codes
DCLK fMAX
(MHz)
(1)
Operation
Write enable
Operation Code
Address Bytes
Dummy Bytes
Data Bytes
0000 0110
0000 0100
0000 0101
0000 0011
1010 1011
0000 1011
0000 0001
0000 0010
1100 0111
0
0
0
3
0
3
0
3
0
0
0
0
0
3
1
0
0
0
0
0
25
25
32
20
32
40
25
25
25
Write disable
Read status
Read bytes
Read silicon ID
Fast read
(2)
1 to infinite
1 to infinite
1 to infinite
1 to infinite
1
(2)
(2)
(2)
(4)
Write status
Write bytes
Erase bulk
(3)
1 to 256
0
Serial Configuration (EPCS) Devices Datasheet
April 2014 Altera Corporation
INTEL [ INTEL ]
