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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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Chapter 1: Cyclone III Device Datasheet  
1–27  
Glossary  
f
The Excel-based I/O Timing spreadsheet is downloadable from Cyclone III Devices  
Literature website.  
Glossary  
Table 1–39 lists the glossary for this chapter.  
Table 1–39. Glossary (Part 1 of 5)  
Letter  
Term  
Definitions  
A
B
C
D
E
F
fHSCLK  
GCLK  
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.  
Input pin directly to Global Clock network.  
G
H
GCLK PLL  
HSIODR  
Input pin to Global Clock network through PLL.  
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).  
VIH  
Input Waveforms  
for the SSTL  
Differential I/O  
Standard  
I
VSWING  
VREF  
VIL  
TMS  
TDI  
tJCP  
tJPSU_TDI  
tJPSU_TMS  
tJCH  
t JCL  
tJPH  
TCK  
TDO  
J
JTAG Waveform  
tJPXZ  
tJPZX  
tJPCO  
tJSSU  
tJSH  
Signal  
to be  
Captured  
tJSZX  
tJSCO  
tJSXZ  
Signal  
to be  
Driven  
K
L
M
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
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