1–28
Chapter 1: Cyclone III Device Datasheet
Glossary
Table 1–39. Glossary (Part 2 of 5)
Letter
Term
—
Definitions
N
O
—
—
—
The following block diagram highlights the PLL Specification parameters.
CLKOUT Pins
fOUT_EXT
Switchover
CLK
fIN
fINPFD
N
fVCO
VCO
PFD
CP
LF
fOUT
GCLK
Counters
Core Clock
C0..C4
P
Q
PLL Block
Phase tap
M
Key
Reconfigurable in User Mode
—
—
RL
Receiver differential input discrete resistor (external to Cyclone III devices).
Receiver Input Waveform for LVDS and LVPECL Differential Standards.
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
Ground
VCM
Receiver Input
Waveform
R
Differential Waveform (Mathematical Function of Positive & Negative Channel)
VID
0 V
VID
p - n
RSKM (Receiver
input skew
margin)
HIGH-SPEED I/O Block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
INTEL [ INTEL ]
