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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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1–26  
Chapter 1: Cyclone III Device Datasheet  
I/O Timing  
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (1), (2) (Part 2 of 2)  
Max Offset  
Number  
Paths  
Affected  
Min  
Offset  
Parameter  
of  
Fast Corner  
A7, I7 C6  
Slow Corner  
C8  
Unit  
Settings  
C6  
C7  
I7  
A7  
I/O output  
register to  
pad  
Delay from output  
register to output pin  
2
0
0
0.479 0.504 0.915 1.011 1.107 1.018 1.048  
0.664 0.694 1.199 1.378 1.532 1.392 1.441  
ns  
ns  
Input delay from  
Pad to global  
dual-purpose clock pin clock  
to fan-out destinations network  
12  
Notes to Table 1–37:  
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.  
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.  
(1), (2)  
Table 1–38. Cyclone III Devices IOE Programmable Delay on Row Pins  
Max Offset  
Number  
Paths  
Affected  
Min  
Offset  
Parameter  
of  
Fast Corner  
A7, I7 C6  
Slow Corner  
C8  
Unit  
Settings  
C6  
C7  
I7  
A7  
Pad to I/O  
dataout to  
core  
Input delay from pin to  
internal cells  
7
8
2
0
0
0
1.209 1.314 2.174 2.335 2.406 2.381 2.505  
1.207 1.312 2.202 2.402 2.558 2.447 2.557  
ns  
ns  
ns  
Input delay from pin to Pad to I/O  
input register  
input register  
I/O output  
register to  
pad  
Delay from output  
register to output pin  
0.51  
0.537 0.962 1.072 1.167 1.074 1.101  
Input delay from  
dual-purpose clock pin  
to fan-out destinations  
Pad to global  
clock network  
12  
0
0.669 0.698 1.207 1.388 1.542 1.403  
1.45  
ns  
Notes to Table 1–38:  
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.  
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software  
I/O Timing  
You can use the following methods to determine the I/O timing:  
the Excel-based I/O Timing.  
the Quartus II timing analyzer.  
The Excel-based I/O Timing provides pin timing performance for each device density  
and speed grade. The data is typically used prior to designing the FPGA to get a  
timing budget estimation as part of the link timing analysis. The Quartus II timing  
analyzer provides a more accurate and precise I/O timing data based on the specifics  
of the design after place-and-route is complete.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
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