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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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Chapter 1: Cyclone III Device Datasheet  
1–15  
Switching Characteristics  
PLL Specifications  
Table 1–20 describes the PLL specifications for Cyclone III devices when operating in  
the commercial junction temperature range (0°C to 85°C), the industrial junction  
temperature range (–40°C to 100°C), and the automotive junction temperature range  
(–40°Cto 125°C). For more information about PLL block, refer to “PLL Block” in  
“Glossary” on page 1–27.  
Table 1–20. Cyclone III Devices PLL Specifications (1)  
(Part 1 of 2)  
Parameter  
Symbol  
Min  
5
Typ  
Max  
472.5  
325  
Unit  
MHz  
MHz  
MHz  
%
(2)  
fIN  
fINPFD  
Input clock frequency  
PFD input frequency  
5
(3)  
fVCO  
PLL internal VCO operating range  
600  
40  
1300  
60  
fINDUTY  
Input clock duty cycle  
Input clock cycle-to-cycle jitter for FINPFD 100 MHz  
Input clock cycle-to-cycle jitter for FINPFD < 100 MHz  
0.15  
750  
UI  
(4)  
tINJITTER_CCJ  
ps  
f
OUT_EXT (external clock output)  
PLL output frequency  
472.5  
MHz  
(2)  
PLL output frequency (–6 speed grade)  
45  
50  
472.5  
450  
402.5  
55  
MHz  
MHz  
MHz  
%
fOUT (to global clock)  
PLL output frequency (–7 speed grade)  
PLL output frequency (–8 speed grade)  
tOUTDUTY  
tLOCK  
Duty cycle for external clock output (when set to 50%)  
Time required to lock from end of device configuration  
1
ms  
Time required to lock dynamically (after switchover,  
reconfiguring any non-post-scale counters/delays or  
areset is deasserted)  
tDLOCK  
1
ms  
Dedicated clock output period jitter  
300  
30  
ps  
mUI  
ps  
(5)  
F
OUT 100 MHz  
tOUTJITTER_PERIOD_DEDCLK  
F
OUT < 100 MHz  
Dedicated clock output cycle-to-cycle jitter  
300  
30  
(5)  
F
OUT 100 MHz  
tOUTJITTER_CCJ_DEDCLK  
F
OUT < 100 MHz  
mUI  
ps  
Regular I/O period jitter  
650  
75  
(5)  
F
OUT 100 MHz  
tOUTJITTER_PERIOD_IO  
F
OUT < 100 MHz  
mUI  
ps  
Regular I/O cycle-to-cycle jitter  
650  
(5)  
F
OUT 100 MHz  
tOUTJITTER_CCJ_IO  
F
OUT < 100 MHz  
10  
75  
50  
mUI  
ps  
tPLL_PSERR  
tARESET  
Accuracy of PLL phase shift  
Minimum pulse width on areset signal.  
ns  
SCANCLK  
cycles  
(6)  
tCONFIGPLL  
Time required to reconfigure scan chains for PLLs  
3.5  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
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