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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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Chapter 1: Cyclone III Device Datasheet  
1–13  
Electrical Characteristics  
(1)  
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications  
(Part 2 of 2)  
VOD (mV)  
(2)  
(3)  
(3)  
VCCIO (V)  
VID (mV)  
VIcM (V)  
VOS (V)  
I/O  
Standard  
Min Typ Max  
Min Max Min  
Condition  
Max Min Typ Max Min Typ Max  
0.05  
DMAX 500 Mbps 1.80  
LVDS  
(Column  
I/Os)  
500 Mbps DMAX  
700 Mbps  
2.375 2.5 2.625 100  
0.55  
1.05  
1.80 247  
1.55  
600 1.125 1.25 1.375  
DMAX > 700 Mbps  
BLVDS  
(Row I/Os) 2.375 2.5 2.625 100  
(5)  
BLVDS  
(Column  
2.375 2.5 2.625 100  
(5)  
I/Os)  
mini-LVDS  
(Row I/Os) 2.375 2.5 2.625  
300  
300  
600  
600  
1.0  
1.0  
0.5  
0.5  
0.5  
0.5  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.4  
1.4  
1.5  
1.5  
1.4  
1.4  
(6)  
mini-LVDS  
(Column  
2.375 2.5 2.625  
2.375 2.5 2.625  
2.375 2.5 2.625  
(6)  
I/Os)  
RSDS®  
(Row  
100 200 600  
100 200 600  
100 200 600  
100 200 600  
I/Os) (6)  
RSDS  
(Column  
(6)  
I/Os)  
PPDS®  
(Row I/Os) 2.375 2.5 2.625  
(6)  
PPDS  
(Column  
2.375 2.5 2.625  
(6)  
I/Os)  
Notes to Table 1–18:  
(1) For an explanation of terms used in Table 1–18, refer to “Transmitter Output Waveform” in “Glossary” on page 1–27.  
(2) VIN range: 0 V VIN 1.85 V.  
(3) RL range: 90 RL 110 .  
(4) LVPECL input standard is only supported at clock input. Output standard is not supported.  
(5) No fixed VIN, VOD, and VOS specifications for BLVDS. They are dependent on the system topology.  
(6) Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins for Cyclone III devices.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
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