28F320J5 and 28F640J5
6.6
AC Characteristics— Write Operations(1,2)
Valid for All
Speeds
Versions
#
Sym
(t
Parameter
RP# High Recovery to WE# (CE ) GoingLow
Notes
Min
Max
Unit
W1
W2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
)
3
4
1
0
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHWL PHEL
X
(t
)
CE (WE#) Low to WE# (CE ) GoingLow
ELWL WLEL
X
X
W3
Write Pulse Width
4
70
50
50
10
0
WP
W4
(t
)
Data Setup to WE# (CE ) GoingHigh
5
DVWH DVEH
X
W5
(t
)
Address Setup to WE# (CE ) GoingHigh
5
AVWH AVEH
X
W6
(t
)
CE (WE#) Hold from WE# (CE ) Hig h
X X
WHEH EHWH
W7
(t
)
Data Hold from WE# (CE ) Hig h
X
WHDX EHDX
W8
(t
)
Address Hold from WE# (CE ) Hig h
0
WHAX EHAX
X
W9
Write Pulse Width Hig h
6
30
0
WPH
W10
W11
W12
W13
W14
W15
(t
)
RP# V Setup to WE# (CE ) GoingHigh
3
3
PHHWH PHHEH
HH
X
(t
)
)
V
Setup to WE# (CE ) GoingHigh
0
VPWH VPEH
PEN
X
(t
Write Recovery before Read
WE# (CE ) Hig h to STS Going Low
7
35
WHGL EHGL
(t
)
8
90
WHRL EHRL
X
RP# V Hold from Valid SRD, STS GoingHigh
3,8,9
3,8,9
0
0
QVPH
QVVL
HH
V
Hold from Valid SRD, STS GoingHigh
PEN
NOTE: CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at
X
0
1
2
X
the first edg e of CE, CE , or CE that disables the device (see Table 2 on pag e 12).
0
1
2
1. Read timingcharacteristics duringblock erase, program, and lock-bit configuration operations are the same
as duringread-only operations. Refer to AC Characteristics–Read-Only Operations.
2. A write operation can be initiated and terminated with either CE or WE#.
X
3. Sampled, not 100% tested.
4. Write pulse width (t ) is defined from CE or WE# going low (whichever goes low last) to CE or WE# going
WP
X
WP
X
high (whichever goes high first). Hence, t
= t
= t
= t
= t
. If CE is driven low 10 ns
WLWH
ELEH
WLEH
ELWH X
before WE# going low, WE# pulse width requirement decreases to t
- 10 ns.
WP
5. Refer to Table 4 on pag e 17for valid A and D for block erase, program, or lock-bit configuration.
IN
IN
6. Write pulse width hig h (t
) is defined from CE or WE# going high (whichever goes high first) to CE or
WPH
X
X
WE# going low (whichever goes low first). Hence, t
= t
= t
= t
= t
.
WPH
WHWL
EHEL
WHEL
EHWL
7. For array access, t
is required in addition to t
for any accesses after a write.
AVQV
WHGL
8. STS timings are based on STS configured in its RY/BY# default mode.
9. V should be held at V (and if necessary RP# should be held at V ) until determination of block
PEN
PENH
HH
erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
46
Datasheet
INTEL [ INTEL ]
