28F320J5 and 28F640J5
6.5
AC Characteristics—Read-Only Operations(1)
Versions
(All units in ns unless otherwise noted)
5 V 10% V
–120/–150(2)
–120/–150(2)
CCQ
2.7 V—10% V
CCQ
#
Sym
Parameter
Notes
Min
Max
120
130 at +85° C
32 Mbit
R1
R2
R3
t
t
t
Read/Write Cycle Time
Address to Output Delay
CEX to Output Delay
AVAV
64 Mbit
32 Mbit
64 Mbit
32 Mbit
64 Mbit
150
120
130 at +85° C
AVQV
ELQV
150
120
130 at +85° C
3
3
3
150
50
R4
R5
t
t
OE# to Output Delay
GLQV
32 Mbit
64 Mbit
180
210
RP# Hig h to Output Delay
PHQV
R6
R7
R8
R9
t
t
t
t
CEX to Output in Low Z
4
4
0
0
ELQX
GLQX
EHQZ
GHQZ
OE# to Output in Low Z
CEX Hig h to Output in Hig h Z
OE# Hig h to Output in Hig h Z
4
4
55
15
Output Hold from Address, CEX, or OE# Change,
Whichever Occurs First
R10
R11
t
4
4
0
OH
t
t
ELFL
CEX Low to BYTE# High or Low
BYTE# to Output Delay
10
ELFH
t
t
FLQV
R12
1000
1000
FHQV
R13
R14
t
t
BYTE# to Output in High Z
CEx Disable Pulse Width
4
4
FLQZ
EHEL
10
NOTE: CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at
X
0
1
2
X
the first edg e of CE, CE , or CE that disables the device (seeTable 2).
0
1
2
1. See Figure 15, “AC Waveform for Read Operations” on page 45 for the maximum allowable input slew rate.
2. See Figure 12, Figure 13, and Fig ure 14 on pag e 4,3for testingcharacteristics
3. OE# may be delayed up to t
-t
.
after the first edge of CE0, CE1, or CE2 that enables the device (see
ELQV GLQV
Table 2) without impact on t
4. Sampled, not 100% tested.
ELQV
44
Datasheet
INTEL [ INTEL ]
