28F320J5 and 28F640J5
Figure 16. AC Waveform for Write Operations
A
B
C
D
E
F
VIH
VIL
AIN
AIN
ADDRESSES [A]
W5
W8
Disabled (VIH
)
CEX, (WE#) [E(W)]
Enabled (VIL)
W6
W12
W1
VIH
OE# [G]
VIL
W2
W9
W16
Disabled (VIH
)
WE#, (CEX) [W(E)]
Enabled (VIL)
W3
W4
High Z
W7
VIH
Valid
SRD
DIN
DIN
DIN
DATA [D/Q]
VIL
W13
VOH
STS [R]
RP# [P]
VOL
VHH
VIH
W10
W14
W15
VIL
W11
VPENH
V
VPEN [VP]ENLK
VIL
0606_17
NOTE: CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at
X
0
1
2
X
the first edg e of CE , CE , or CE that disables the device (see Table 2 on pag e 12). STS is shown in its
0
1
2
default mode (RY/BY#).
a. V power-up and standby.
CC
b. Write block erase, write buffer, or program setup.
c. Write block erase or write buffer confirm, or valid address and data.
d. Automated erase delay.
e. Read status register or query data.
f. Write Read Array command.
Datasheet
47
INTEL [ INTEL ]
