28F320J5 and 28F640J5
Figure 17. AC Waveform for Reset Operation
VIH
STS (R)
VIL
P2
VIH
RP# (P)
VIL
P1
0606_18
NOTE: STS is shown in its default mode (RY/BY#).
Table 21. Reset Specifications(1)
#
Sym
Parameter
Notes Min
Max
RP# Pulse Low Time
P1
t
2
3
35
PLPH
(If RP# is tied to V , this specification is not applicable)
CC
RP# Hig h to Reset during Block Erase, Prog ram, or Lock-Bit
Configuration
P2
t
100
PHRH
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RP# Pulse Low Time is 100 ns.
3. A reset time, t
valid.
, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are
PHQV
48
Datasheet
INTEL [ INTEL ]
