28F320J5 and 28F640J5
DC Characteristics, Continued
Symbol
Parameter
Input Low Voltage
Notes
Min
Max
Unit
Test Conditions
V
5
–0.5
0.8
V
IL
V
CC
V
V
Input High Voltage
Output Low Voltage
5
2.0
V
IH
OL
+ 0.5
0.45
0.4
2,5
V
V
V
V
V
= V
= V
= V
Min, I = 5.8 mA
OL
CCQ
CCQ
CCQ
CCQ1
CCQ2
CCQ1
Min, I = 2 mA
OL
Min or V
= V
Min
CCQ
CCQ2
V
Output High Voltage
3,7
2.4
V
V
I
= –2.5 mA (V
)
CCQ1
OH
OH
–2 mA (V
)
CCQ2
V
I
= V
Min or V
Min or V
= V
= V
Min
Min
0.85 X
CCQ
CCQ1
CCQ
CCQ
CCQ2
V
= –2.5 mA
CCQ
OH
V
= V
CCQ1
V
–0.4
CCQ
CCQ2
CCQ
V
V
I
= –100 µA
OH
V
Lockout duringNormal
PEN
V
5,7,8
3.6
PENLK
Operations
V
duringBlock Erase,
PEN
V
V
V
7,8
9
4.5
5.5
V
V
V
PENH
LKO
HH
Program, or Lock-Bit Operations
V
Lockout Voltage
3.25
11.4
CC
Set master lock-bit
Override lock-bit
RP# Unlock Voltage
10,11
12.6
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages
and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical
specifications.
2. Includes STS.
3. CMOS inputs are either V
4. Add 5 mA for V
0.2 V or GND 0.2 V. TTL inputs are either V or V .
IL IH
min.
CC
CCQ2
= V
CCQ
5. Sampled, not 100% tested.
6. I
the device’s current draw is I
is specified with the device de-selected. If the device is read or written while in erase suspend mode,
CCES
or I
.
CCR
CCW
7. Tie V
to V (4.5 V–5.5 V).
PEN
CC
8. Block erases, programming, and lock-bit configurations are inhibited when V
guaranteed in the range between V
9. Block erases, programming, and lock-bit configurations are inhibited when V < V
≤ V
PENH
, and not
PENLK
(max).
PEN
(max) and V
(min), and above V
PENLK
PENH
, and not guaranteed
CC
LKO
in the range between V
(min) and V (min), and above V (max).
LKO
CC CC
10.Master lock-bit set operations are inhibited when RP# = V . Block lock-bit configuration operations are
IH
inhibited when the master lock-bit is set and RP# = V . Block erases and programming are inhibited when
the correspondingblock-lock bit is set and RP# = V . Block erase, program, and lock-bit configuration
operations are not guaranteed and should not be attempted with V < RP# < V
IH
IH
.
IH
HH
11.RP# connection to a V supply is allowed for a maximum cumulative period of 80 hours.
HH
42
Datasheet
INTEL [ INTEL ]
