28F320J5 and 28F640J5
Figure 15. AC Waveform for Read Operations
Device
Address Selection
Standby
VIH
Data Valid
Address Stable
ADDRESSES [A]
VIL
R1
R14
R8
Disabled (V )
CEX [E]
IH
Enabled (V )
IL
R2
R3
VIH
OE# [G]
VIL
R9
VIH
R4
WE# [W]
VIL
R10
R5
High Z
R6
VOH
VOL
DATA [D/Q]
DQ0-DQ15
High Z
Valid Output
R7
VIH
VCC
VIL
VIH
RP# [P]
R11
R12
VIL
VIH
R13
BYTE# [F]
VIL
0606_16
NOTE: CE low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE high is defined at
X
X
the first edg e of CE, CE1, or CE2 that disables the device (see Table 2, “Chip Enable Truth Table” on
0
page 12).
Datasheet
45
INTEL [ INTEL ]
