28F320J5 and 28F640J5
Figure 12. Transient Input/Output Reference Waveform for VCCQ = 5.0 V 10% (Standard
Testing Configuration)
2.4
2.0
0.8
2.0
Output
0.8
Input
Test Points
0.45
NOTE: AC test inputs are driven at V
(2.4 V
) for a Logic “1” and V (0.45 V
TTL OL TTL
) for a Logic "0." Input timing begins at
OH
V
(2.0 V
) and V (0.8 V
). Output timingends at V and V . Input rise and fall times (10% to 90%) <10 ns.
IH
TTL IL TTL
IH IL
Figure 13. Transient Input/Output Reference Waveform
2.7
Input
1.35
Test Points
1.35 Output
0.0
NOTE: AC test inputs are driven at 2.7 V for a Logic “1” and 0.0 V for a Logic “0.” Input timing begins, and output timing ends,
at 1.35 V (50% of V ). Input rise and fall times (10% to 90%) <10 ns.
CCQ
Figure 14. Transient Equivelent Testing Load Circuit
1.3V
1N914
RL = 3.3 k
Ω
Device
Under Test
Out
CL
NOTE:
C Includes JigCapacitance
L
Table 20. Test Configuration Capacitance Loading Value
Test Configuration
C (pF)
L
V
V
= 5.0 V ± 10%
= 2.7 V−3.6 V
100
50
CCQ
CCQ
Datasheet
43
INTEL [ INTEL ]
