Networking Silicon — 82551IT
5.2.1.1.2 Flash Buffer Accesses
The CPU accesses to the Flash buffer are very slow and the 82551IT issues a target-disconnect at
the first data access. The 82551IT asserts the STOP# signal to indicate a target-disconnect. The
figures below illustrate memory CPU read and write accesses to the 128 KB Flash buffer. The
longest burst cycle to the Flash buffer contains one data access only.
Figure 4. Flash Buffer Read Cycle
CLK
FRAME#
AD
ADDR
DATA
MEM RD
BE#
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
Read Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551IT controls the
TRDY# signal and de-asserts it for a certain number of clocks until valid data can be read from the
Flash buffer. When TRDY# is asserted, the 82551IT drives valid data on the AD[31:0] lines. The
CPU can also insert wait states by de-asserting IRDY# until it is ready. Flash buffer read accesses
can be byte or word length.
Datasheet
19
INTEL [ INTEL ]
