Networking Silicon — 82551IT
5.2.1.1.1 Control/Status Register (CSR) Accesses
The 82551IT supports zero wait state single cycle memory or I/O mapped accesses to its CSR
space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space to accomplish
these accesses. The 82551IT provides 4 valid KB of CSR space, which include the following
elements:
• System Control Block (SCB) registers
• PORT register
• Flash control register
• EEPROM control register
• MDI control register
• Flow control registers
The following figures show CSR zero wait state I/O read and write cycles. In the case of accessing
the Control/Status Registers, the CPU is the initiator and the 82551IT is the target of the
transaction.
Figure 2. CSR I/O Read Cycle
CLK
1
2
3
4
5
6
7
8
9
FRAME#
AD
ADDR
I/O RD
DATA
BE#
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte
enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. As a slave, the 82551IT
controls the TRDY# signal and provides valid data on each data access. The 82551IT allows the
CPU to issue only one read cycle when it accesses the Control/Status Registers, generating a
disconnect by asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY#
when it is not ready.
Datasheet
17
INTEL [ INTEL ]
