82551IT — Networking Silicon
Figure 3. CSR I/O Write Cycle
CLK
1
2
3
4
5
6
7
8
9
FRAME#
AD
ADDR
DATA
I/O WR
BE#
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the
82551IT with valid data on each data access immediately after asserting IRDY#. The 82551IT
controls the TRDY# signal and asserts it from the data access. The 82551IT allows the CPU to
issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting
the STOP# signal. This is true for both memory mapped and I/O mapped accesses.
18
Datasheet
INTEL [ INTEL ]
