Networking Silicon — 82551IT
command for burst accesses to control structures. For all write accesses to the control structure, the
82551IT uses the Memory Write (MW) command. For write accesses to data structure, the
82551IT may use either the Memory Write or Memory Write and Invalidate (MWI) commands.
Read Accesses: The 82551IT performs block transfers from host system memory to perform frame
transmission on the serial link. In this case, the 82551IT initiates zero wait state memory read burst
cycles for these accesses. The length of a burst is bounded by the system and the 82551IT’s internal
FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA
Maximum Byte Count in the Configure command. The Transmit DMA Maximum Byte Count
value indicates the maximum number of transmit DMA PCI cycles that will be completed after an
82551IT internal arbitration.
The 82551IT, as the initiator, drives the address lines AD[31:0], the command and byte enable
lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551IT asserts IRDY# to
support zero wait state burst cycles. The target signals the 82551IT that valid data is ready to be
read by asserting the TRDY# signal.
Write Accesses: The 82551IT performs block transfers to host system memory during frame
reception. In this case, the 82551IT initiates memory write burst cycles to deposit the data, usually
without wait states. The length of a burst is bounded by the system and the 82551IT’s internal FIFO
threshold. The length of a write burst may also be bounded by the value of the Receive DMA
Maximum Byte Count in the Configure command. The Receive DMA Maximum Byte Count value
indicates the maximum number of receive DMA PCI transfers that will be completed before the
82551IT internal arbitration.
The 82551IT, as the initiator, drives the address lines AD[31:0], the command and byte enable
lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551IT asserts IRDY# to
support zero wait state burst cycles. The 82551IT also drives valid data on AD[31:0] lines during
each data phase (from the first clock and on). The target controls the length and signals completion
of a data phase by de-assertion and assertion of TRDY#.
5.2.1.2.1 Memory Write and Invalidate
The 82551IT has four Direct Memory Access (DMA) channels. Of these four channels, the
Receive DMA is used to deposit the large number of data bytes received from the link into system
memory. The Receive DMA uses both the Memory Write (MW) and the Memory Write and
Invalidate (MWI) commands. To use MWI, the 82551IT must guarantee the following:
1. Minimum transfer of one cache line
2. Active byte enable bits (or BE[3:0]# are all low) during MWI access
3. The 82551IT may cross the cache line boundary only if it intends to transfer the next cache
line too.
To ensure the above conditions, the 82551IT may use the MWI command only if the following
conditions are true:
1. The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16
Dwords.
2. The accessed address is cache line aligned.
3. The 82551IT has at least 8 or 16 Dwords of data in its receive FIFO.
4. There are at least 8 or 16 Dwords of data space left in the system memory buffer.
5. The MWI Enable bit in the PCI Configuration Command register, bit 4, must be set to 1b.
Datasheet
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INTEL [ INTEL ]
