Networking Silicon — 82551IT
5.2.1.1.3 Retry Premature Accesses
The 82551IT responds with a Retry to any configuration cycle accessing the 82551IT before the
completion of the automatic read of the EEPROM. The 82551IT may continue to Retry any
configuration accesses until the EEPROM read is complete. The 82551IT does not enforce the rule
that the retry master must attempt to access the same address again to complete any delayed
transaction. Any master access to the 82551IT after the completion of the EEPROM read will be
honored. Figure 6 below shows how a Retry looks when it occurs.
Figure 6. PCI Retry Cycle
CLK
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
Note: The 82551IT is considered the target in the above diagram; thus, TRDY# is not asserted.
5.2.1.1.4 Error Handling
Data Parity Errors: The 82551IT checks for data parity errors while it is the target of the
transaction. If an error was detected, the 82551IT always sets the Detected Parity Error bit in the
PCI Configuration Status register, bit 15. The 82551IT also asserts PERR#, if the Parity Error
Response bit is set (PCI Configuration Command register, bit 6). The 82551IT does not attempt to
terminate a cycle in which a parity error was detected. This gives the initiator the option of
recovery.
Target-Disconnect: The 82551IT prematurely terminates a cycle in the following cases:
• After accesses to the Flash buffer
• After accesses to its CSR
• After accesses to the configuration space
System Error: The 82551IT reports parity error during the address phase using the SERR# pin. If
the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit
is not set, the 82551IT only sets the Detected Parity Error bit (PCI Configuration Status register, bit
15). If SERR# Enable and Parity Error Response bits are both set, the 82551IT sets the Signaled
System Error bit (PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit
and asserts SERR# for one clock.
Datasheet
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INTEL [ INTEL ]
