82551IT — Networking Silicon
Figure 5. Flash Buffer Write Cycle
CLK
FRAME#
DATA
BE#
ADDR
AD
MEM WR
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the 82551IT
with valid data immediately after asserting IRDY#. The 82551IT controls the TRDY# signal and de-
asserts it for a certain number of clocks until valid data is written to the Flash buffer. By asserting
TRDY#, the 82551IT signals the CPU that the current data access has completed. Flash buffer write
accesses can be byte length only.
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Datasheet
INTEL [ INTEL ]
